1. Field of the Invention
The present invention relates to semiconductor fabrication and, more particularly, to an improved method for creating mask patterns for use in lithographic processing of integrated circuits (ICs).
2. Background and Related Art
Integrated circuits are fabricated by lithographic techniques where energy beams transmit integrated circuit images or patterns on photomasks onto photosensitive resists on semiconductor wafer substrates. This lithographic transfer of mask patterns into photoresist, development of the photoresist, followed either by ion implant or etch processes is a standard process for creating chips. However, this process is not only limited in its pattern fidelity due to the small size of the patterns being printed relative to the wavelength of the light used, but it is also limited by a variety of other nonlinear effects involved in the overall process. Thus, in addition to the limited resolution of the optical image process, the shortcomings of the pattern transfer process used to build a mask, the nonlinear nature of the chemical processes within the resist and during developing as well as pattern density dependencies of the etch process, all contribute to distorting the final on wafer result relative to the original design.
Optical proximity correction is a methodology by which the distortions of the pattern transfer process are corrected such that the final on-wafer result resembles as close as possible the desired design. This is accomplished by creating a more or less empirical model that describes all the above mentioned process effects, carefully characterizing the process and using this model to modify the pattern on the reticule relative to the original design such as to counteract the distortions.
Optical Proximity Correction (OPC) has thus been employed as a key enabling resolution enhancement technique required to meet image size control requirements imposed by state-of-the-art integrated circuit product programs. OPC, then, is essentially the deliberate and proactive distortion of photomask patterns to compensate for systematic and stable errors. OPC is generally categorized as either rules-based or model-based. Rules-based OPC is accomplished by determining the correctable imaging errors, calculating appropriate photomask compensations, and finally applying the calculated corrections directly to the photomask layout. While proven to be efficient at correcting some important one- and two-dimensional imaging problems, non-iterative rules based OPC is generally believed limited in its usefulness due to the finite number of rules that are available to describe all layout situations, the difficulty of calculating exact correction values based on measured errors, and the lack of feedback loop during the correction process.
Existing model-based OPC tools overcome some of these shortcomings by employing an iterative optimization approach. Model-based OPC is predicated on the concept of capturing the imaging characteristics in a mathematical model, or a combination of mathematics and heuristics, and calculating only the expected or predicted on-wafer circuit image which would be projected by the mask pattern under investigation. The correction to be applied is never directly calculated. Rather, the correction is derived by comparing the simulated predicted image contour placement to the edge placement of the original mask pattern and iteratively adjusting until a match or near match is found or until all iterations are exhausted. An example of such process has been described in U.S. Pat. No. 6,578,190.
The goal of the most common approaches to modifying mask patterns, whether it be rules-based or mode-based, is to ensure the layout patterns are replicated within the specifications assumed by the circuit designer. In some cases, efforts have been made to ensure that the patterns are reproduced over the largest possible lithographic process window (i.e., range of dose and defocus). However, this approach still results in deficiencies in producing circuit patterns. Circuit layout follows a set of design rules that specify limits and allowed ranges of pattern dimensions. Due to the strong desire to provide the smallest chip dimensions possible, certain minimum geometries might be allowed in the design rules even though they may not be optimum to achieve the highest yield. Quite frequently the particular layout chosen is dictated by convenience rather than optimum yield or space restriction. Minimum geometries are chosen due to limitations in the automated layout generators rather than space restrictions. Thus, it is highly desirable to eliminate such yield limiting geometries wherever they are not absolutely required.
Thus, although the design chosen is one based upon a generic set of design rules that have been established to eliminate layout geometries that cause failure, non-perfect automation tools used to create the layout and the fact that design rules have been written with the most generic design in mind, most layout designs can be further modified from the circuit designers' layout version to one that is more optimized in terms of yield. Accordingly, process results that show failure mechanisms due to circuit layout geometries within the generic set of design rules may be translated into yield functions that can be used to further define and optimize changes to the mask layout in a model-based OPC tool.